Senior/Staff Design for Test EngineerEmbedded

{
  "source": {
    "name": "linkedin",
    "id": "4408405731",
    "url": "https://www.linkedin.com/jobs/view/senior-staff-design-for-test-engineer-at-olix-4408405731?_l=en"
  },
  "postedDate": "2026-05-05T15:44:01.660Z",
  "applicationDeadline": null,
  "isActive": true,
  "isExpired": false,
  "matching": {
    "role": {
      "primaryTitle": "Senior/Staff Design for Test Engineer",
      "titleSynonyms": [
        "Design for Test Engineer",
        "Senior Design for Test Engineer",
        "Staff Design for Test Engineer"
      ],
      "secondaryTitles": [
        "DFT Engineer",
        "ASIC Design Engineer"
      ],
      "function": "science_engineering_professionals",
      "functionConfidence": "high",
      "roleFamily": "u2149_engineering_professionals_nec",
      "roleFamilyConfidence": "medium",
      "roleSubFamily": "Design for Test",
      "roleSubFamilyConfidence": "medium",
      "seniority": "mid_senior",
      "industries": [
        "i56_mining"
      ]
    },
    "primarySignals": {
      "tasks": [
        "Architect and implement Design-for-Test (DFT) strategy for high-throughput digital pipelines",
        "Lead integration and verification of DFT features including Scan, JTAG, Boundary Scan, Memory BIST",
        "Develop and optimize ATE-compatible test patterns to maximize fault coverage and yield",
        "Drive RTL development focusing on DFT architecture and synthesis constraints",
        "Analyze and minimize DFT impact on power, performance, and area",
        "Collaborate on DFT interfaces, test modes, and firmware abstractions",
        "Mentor junior engineers and lead DFT design reviews"
      ],
      "skills": [
        "Design for Test (DFT) architecture and implementation",
        "Verification of DFT features",
        "Scan insertion and ATPG",
        "Pattern simulation and fault modeling",
        "Compression techniques and EDT",
        "JTAG/IEEE 1149.1/1687 standards",
        "Python and Tcl scripting for automation",
        "Semiconductor device physics and fault models"
      ],
      "tools": [
        "SystemVerilog",
        "Verilog",
        "VHDL",
        "EDA flows for Scan insertion, ATPG, pattern simulation",
        "Python",
        "Tcl"
      ],
      "educationLevel": null,
      "educationKeywords": [
        "Semiconductor device physics"
      ],
      "certifications": [],
      "languages": [],
      "yearsRelevant": 7
    },
    "secondarySignals": {
      "tasks": [
        "Tape-out experience at 22 nm or below",
        "Knowledge of high-speed SerDes or HBM/DDR DFT challenges",
        "Familiarity with AI/ML workloads or systolic arrays",
        "Contributions to open-source DFT tools or verification frameworks"
      ],
      "skills": [],
      "tools": [],
      "educationLevel": null,
      "educationKeywords": [],
      "certifications": [],
      "languages": [],
      "yearsRelevant": null
    },
    "practical": {
      "locations": [
        "Bristol, England, United Kingdom"
      ],
      "locationProvenance": "stated",
      "countries": [
        "GB"
      ],
      "workModes": [
        "unknown"
      ],
      "workModeProvenance": "defaulted",
      "employmentTypes": [
        "full_time"
      ],
      "compensation": null
    },
    "dataCompleteness": "high"
  },
  "indexing": {
    "function": "science_engineering_professionals",
    "functionConfidence": "high",
    "roleFamily": "u2149_engineering_professionals_nec",
    "roleFamilyConfidence": "medium",
    "countryCode": "GB",
    "countryCodeConfidence": "high",
    "locationBucket": "ttwa_bristol",
    "locationBucketConfidence": "high",
    "workMode": "unknown",
    "workModeConfidence": "unknown",
    "employmentType": "full_time",
    "employmentTypeConfidence": "high",
    "isAgency": "unknown",
    "salaryMax": null,
    "industryGroup": "i56_mining",
    "industryGroupConfidence": "low",
    "educationRequired": null,
    "educationRequiredConfidence": "unknown"
  },
  "display": {
    "title": "Senior/Staff Design for Test Engineer",
    "company": {
      "name": "OLIX"
    },
    "locationDisplay": "Bristol, England, United Kingdom",
    "applicationUrl": null
  },
  "roleFamilyEsco": "u2149_engineering_professionals_nec",
  "requirementsEssentiality": {
    "items": [
      {
        "text": "7+ years of hands‑on DFT architecture, implementation, and verification for high‑performance ASICs or SoCs",
        "category": "skill",
        "essentiality": "compulsory",
        "triggerPhrase": "Skills & Experience",
        "confidence": "high"
      },
      {
        "text": "ownership of at least one product with comprehensive DFT coverage",
        "category": "skill",
        "essentiality": "compulsory",
        "triggerPhrase": "Skills & Experience",
        "confidence": "high"
      },
      {
        "text": "Proven success implementing and verifying advanced DFT features (e.g., Scan/ATPG, Boundary Scan, Memory BIST/Repair)",
        "category": "skill",
        "essentiality": "compulsory",
        "triggerPhrase": "Skills & Experience",
        "confidence": "high"
      },
      {
        "text": "Expertise with industry‑standard EDA flows: Scan insertion, ATPG, pattern simulation (gate-level), fault modeling, and  ",
        "category": "skill",
        "essentiality": "compulsory",
        "triggerPhrase": "Skills & Experience",
        "confidence": "high"
      },
      {
        "text": "Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern ",
        "category": "skill",
        "essentiality": "compulsory",
        "triggerPhrase": "Skills & Experience",
        "confidence": "high"
      },
      {
        "text": "Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-",
        "category": "skill",
        "essentiality": "compulsory",
        "triggerPhrase": "Skills & Experience",
        "confidence": "high"
      },
      {
        "text": "Solid grounding in semiconductor device physics, fault models (stuck-at, transition, bridging), and yield enhancement ",
        "category": "skill",
        "essentiality": "compulsory",
        "triggerPhrase": "Skills & Experience",
        "confidence": "high"
      },
      {
        "text": "Tape‑out experience at 22 nm or below",
        "category": "skill",
        "essentiality": "preferred",
        "triggerPhrase": "Nice to have",
        "confidence": "high"
      },
      {
        "text": "Knowledge of high-speed SerDes or HBM/DDR DFT challenges",
        "category": "skill",
        "essentiality": "preferred",
        "triggerPhrase": "Nice to have",
        "confidence": "high"
      },
      {
        "text": "Familiarity with AI/ML workloads or systolic arrays and their implications for DFT",
        "category": "skill",
        "essentiality": "preferred",
        "triggerPhrase": "Nice to have",
        "confidence": "high"
      },
      {
        "text": "Contributions to open‑source DFT tools or verification frameworks",
        "category": "skill",
        "essentiality": "preferred",
        "triggerPhrase": "Nice to have",
        "confidence": "high"
      }
    ]
  }
}